This invention relates to dual port random-access-memory circuits, and more particularly, to dual port random-access memory circuits with clamping circuitry to limit maximum bit line voltage swings in read bit lines during concurrent read and write operations.
Dual port memory arrays are used in integrated circuits such as integrated circuit memories and programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices generally contain arrays of random-access memory (RAM). These memory arrays, which are sometimes referred to as embedded array blocks (EABs) are used to handle the storage needs of the circuitry on the device. During normal operation of a programmable logic device, the hardwired and programmable circuitry of the device performs read and write operations on the memory of the blocks. Memory arrays on a programmable logic device typically range in size from a few kilobits to about a megabit or more.
Integrated circuits such as programmable logic devices are often configured to implement memory-based circuits such as clock conversion first-in-first-out (FIFO) circuits. In a typical scenario, data is written into a FIFO using one clock signal and is read out of the FIFO using another clock signal.
Circuits such as FIFO circuits on programmable logic devices are implemented using dual port random-access-memory arrays. Dual port memory arrays are also used in application specific integrated circuits and stand-alone memory chips.
Dual port memory arrays have two independent ports, which can be used for read and write operations. On programmable logic device integrated circuits with dual port memory arrays, programmable logic circuitry and a dual port memory array can be configured to implement a FIFO. One of the dual port memory array's ports is used for write operations, while the other of the dual port memory array's ports is used for read operations.
Dual port memory arrays contain rows and columns of memory cells. Dual port memory array cells are accessed using word lines and bit lines. Because there are two ports associated with each cell, there are two sets of word lines and two sets of bit lines associated with each memory array.
Normal operation of a dual port memory can be disrupted if a write operation on one port occurs during a read operation on the other port.
One way to avoid this type of overlap between read and write operations involves using a common clock for both ports. When a common clock is used, read and write operations can be performed using distinct clock phases, thereby preventing undesirable overlap. However, certain applications such as clock conversion FIFO circuits involve two independent clocks. If it is desired to implement a FIFO circuit of this type, it is not possible to use a common clock for the two ports of the dual port memory array.
Another way to address the disruptions involved when read and write operations overlap involves extending the write clock period. When a longer write clock period is used, the memory cell is less likely to function improperly when a write operation overlaps a read operation.
However, the use of an enlarged write clock cycle slows circuit operation. Moreover, larger write clock cycles will not always ensure proper operation of a memory cell, particularly when the memory cell exhibits large variations due to changes in process, voltage, and temperature (so-called PVT variations). As device sizes and operating voltages become smaller with successive generations of semiconductor manufacturing technology, PVT variations become increasingly important and are expected to be responsible for a growing portion of memory array operational failures such as the disruptions that arise during concurrent read and write operations.
It would therefore be desirable to be able to avoid the deleterious effects of concurrent write and read operations in a dual port memory array without using enlarged write clock cycles.